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industrial power control final data sheet rev 2.0, 2012-07-31 1ED020I12-BT single igbt driver ic eicedriver?
edition 2012-07-31 published by infineon technologies ag 81726 munich, germany ? 2012 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infineo n technologies hereby disclaims any and all warranties and liabilities of any kind, including wit hout limitation, warranties of non-infringement of in tellectual property rights of any third party. information for further information on technology , delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contai n dangerous substances. for information on the types in question, please contact the neares t infineon technologies office. infineon technologies components may be used in life-s upport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
eicedriver? 1ED020I12-BT final data sheet 3 rev 2.0, 2012-07-31 trademarks of infineon technologies ag aurix?, bluemoon?, c166?, ca npak?, cipos?, cipurse?, comn eon?, econopack?, coolmos?, coolset?, corecontrol?, crossave?, dave?, easypim?, econobri dge?, econodual?, econopim?, eicedriver?, eupec?, fcos?, hitfe t?, hybridpack?, i2rf?, isoface?, isopack?, mipaq?, modstack?, my-d?, novalithic?, omnitune?, optimos?, origa?, primarion?, primepack?, primestack?, pr o-sil?, profet?, rasic?, re versave?, satric?, sieget?, sindrion?, sipmos?, smarti?, smartlew is?, solid flash?, tempfet?, thinq!?, trenchstop?, tricore?, x-go ld?, x-pmu?, xmm?, xposys?. other trademarks advance design system? (ads) of agilent te chnologies, amba?, arm?, multi-ice?, keil?, primecell?, realview?, thumb?, vision? of arm limited, uk. autosar? is licensed by autosar development partnership. bluetooth? of bluetooth sig inc. cat-iq? of dect forum. colossus?, firstgps? of trimble navigation ltd. emv? of emvc o, llc (visa holdings in c.). epcos? of epcos ag. flexgo? of microsoft corp oration. flexray? is licensed by flexray consortium. hyperterminal? of hilgraeve incorporated. iec? of commission electrot echnique internationale. irda? of infrared data association corporation. iso? of international organization for standardization. matlab? of mathworks, inc. maxim? of maxim integrated products, inc. microtec?, nucleus? of mentor graphics corporation. mifare? of nx p. mipi? of mipi alliance, inc. mips? of mips technologies, inc., usa. murata? of murata manufacturing co., microwave offi ce? (mwo) of applied wave research inc., omnivision? of omnivision technologies, inc. open wave? openwave systems inc. red hat? red hat, inc. rfmd? rf micro devices, inc. sirius? of sirius sate llite radio inc. solaris? of sun microsystems, inc. spansion? of spansion llc ltd. symbian? of sy mbian software limited. taiyo yuden? of taiyo yuden co. teaklite? of ceva, inc. t ektronix? of tektroni x inc. toko? of toko kabushiki kaisha ta. unix? of x/open company limited. verilog?, palladium? of cadence design systems, inc. vlynq? of texas instruments inco rporated. vxworks?, wind river? of wind river systems, inc. zetex? of diodes zetex limited. last trademarks update 2010-10-26 revision history page or item subjects (major changes since previous revision) rev 2.0, 2012-07-31
eicedriver? 1ED020I12-BT final data sheet 4 rev 2.0, 2012-07-31 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 pin configuration and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3 internal protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3.1 undervoltage lockout (uvlo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3.2 ready status output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3.3 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3.4 active shut-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.4 non-inverting and inverting inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.5 driver output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.6 two-level turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.7 minimal on time / off time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.8 external protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.8.1 desaturation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.8.2 active miller clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.8.3 short circuit clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.9 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 operating parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.3 recommended operating parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.4.1 voltage supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.4.2 logic input and output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.4.3 gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.4.4 active miller clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.4.5 short circuit clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.4.6 dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.4.7 desaturation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.4.8 active shut down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4.9 two-level turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 insulation characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.1 certified according to din en 60747-5-2 (vde 0884 teil 2): 2003-01. basic insulation . . . . . . . . . . 26 6.2 certified according to ul 1577 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.3 reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table of contents
eicedriver? 1ED020I12-BT final data sheet 5 rev 2.0, 2012-07-31 9 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.1 reference layout for thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.2 printed circuit board guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
eicedriver? 1ED020I12-BT final data sheet 6 rev 2.0, 2012-07-31 figure 1 typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2 block diagram 1ED020I12-BT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3 pin configuration pg-dso-16-15 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4 application example bipolar supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5 application example unipolar supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 6 propagation delay, rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 7 principle switching behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 8 typical switching behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 9 desat switch-off behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 10 short switch on pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 11 short switch off pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 12 short switch off pulses, ringing su rpression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 13 vcc2 ramp up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 14 vcc2 ramp down and vcc2 drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 15 typical t tlset time over c tlset capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 16 pg-dso-16-15 (plastic (green) dual small outline package) . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 17 reference layout for ther mal data (copper thickness 102 m) . . . . . . . . . . . . . . . . . . . . . . . . . . 33 list of figures
eicedriver? 1ED020I12-BT final data sheet 7 rev 2.0, 2012-07-31 table 1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 2 absolute maximum ra tings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 3 operating parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 4 recommended operating parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5 voltage supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 6 logic input and output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7 gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 8 active miller clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 9 short circuit clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 10 dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 11 desaturation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 12 active shut down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 13 two-level turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 14 according to din en 60747-5-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 15 according to ul 1577 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 list of tables
product name gate drive current package 1ED020I12-BT 2a pg-dso-16-15 eicedriver? single igbt driver ic 1ED020I12-BT final data sheet 8 rev 2.0, 2012-07-31 1overview main features ? single channel isolated igbt driver ? for 600 v/1200 v igbts ? 2 a rail-to-rail output ? vcesat-detection ? active miller clamp ? two level turn off product highlights ? coreless transformer isolated driver ? basic insulation according to din en 60747-5-2 ? integrated protection features ? suitable for operation at high ambient temperature typical application ? inverters for motor drives ? ups systems ? welding description the 1ED020I12-BT is a galvanic isolated single channel ig bt driver in pg-dso-16-15 package that provides an output current capability of typically 2a. all logic pins are 5v cmos compatible and coul d be directly connected to a microcontroller. the data transfer across galvanic isolation is realiz ed by the integrated coreless transformer technology. the 1ED020I12-BT provides several protection features lik e igbt two level turn off, des aturation prot ection, active miller clamping and active shut down.
eicedriver? 1ED020I12-BT overview final data sheet 9 rev 2.0, 2012-07-31 figure 1 typical application desat clamp tlset out cpu in+, in-, /rst /flt, rdy vcc1 vcc2_h vee2_h gnd2 input side output side gnd1 desat clamp tlset out vcc1 vcc2_l vee2_l gnd2 gnd1 in+, in-, /rst /flt, rdy eicedriver tm 1ED020I12-BT 1ED020I12-BT eicedriver tm
eicedriver? 1ED020I12-BT block diagram final data sheet 10 rev 2.0, 2012-07-31 2 block diagram figure 2 block diagram 1ED020I12-BT gnd1 in+ in- rdy /rst /flt vcc1 10 11 12 13 14 15 9 7 6 5 4 3 2 vcc2 out gnd2 clamp desat tlset delay tx rx decoder uvlo tx vee2 2v encoder 500a 9v k3 & delay 1 flt vcc1 vcc1 vcc1 vcc1 & & delay 1 q s r /rdy 1 1 1 fltnl rst uvlo rx & vee2 1 & vcc2 rdy2 flt2 16 1 8 vee2 gnd1 vee2 k4 vcc2 1ED020I12-BT osc 20mhz vcc2 7v 500a logic s r q vee2
eicedriver? 1ED020I12-BT pin configuration and functionalitypin configuration final data sheet 11 rev 2.0, 2012-07-31 3 pin configuration and functionality 3.1 pin configuration figure 3 pin configuration pg-dso-16-15 (top view) table 1 pin configuration pin no. name function 1 vee2 negative power supply output side 2 desat desaturation protection 3 gnd2 signal ground output side 4 tlset two level set 5 vcc2 positive power supply output side 6 out driver output 7 clamp miller clamping 8 vee2 negative power supply output side 9 gnd1 ground input side 10 in+ non inverted driver input 11 in- inverted driver input 12 rdy ready output 13 /flt fault output, low active 14 /rst reset input, low active 15 vcc1 positive power supply input side 16 gnd1 ground input side vee2 in+ in- rdy /rst /flt vcc1 gnd1 vcc2 out gnd2 clamp desat tlset 1 2 3 4 5 9 16 15 14 13 12 11 gnd1 10 7 8 6 vee2
eicedriver? 1ED020I12-BT pin configuration and func tionalitypin functionality final data sheet 12 rev 2.0, 2012-07-31 3.2 pin functionality gnd1 ground connection of the input side. in+ non inverting driver input in+ control signal for the driver output if in- is set to low. (the igbt is on if in+ = high and in- = low) a minimum pulse width is defined to make the ic robust against glitches at in+. an internal pull- down-resistor ensures igbt off-state. in- inverting driver input in- control signal for driver output if in+ is set to high. (igbt is on if in- = low and in+ = high) a minimum pulse width is defined to make the ic robust against glitches at in-. an internal pu ll-up-resistor ensures igbt off-state. /rst reset input function 1 : enable/shutdown of the input chip. (the igbt is o ff if /rst = low). a minimum pulse width is defined to make the ic robust against glitches at /rst. function 2 : resets the desat-fault-state of the chip if /rst is low for a time t rst . an internal pull-up-resistor is used to ensure /flt status output. /flt fault output open-drain output to report a desaturation error of the igbt (/flt is low if desaturation occurs) rdy ready status open-drain output to report the correct operation of the device (rdy = high if both chips are above the uvlo level and the internal chip transmission is faultless). vcc1 5 v power supply of the input chip vee2 negative power su pply pins of the output chip. if no negative supp ly voltage is available, all vee2 pins have to be connected to gnd2. desat desaturation detection input monitoring of the igbt saturation voltage (v ce ) to detect desaturation caused by short circuits. if out is high, v ce is above a defined value and a certain blanking time has expired, the desaturation protection is activated and the igbt is switched off. the blanking time is adjustable by an external capacitor. clamp miller clamping ties the gate voltage to ground after the igbt has bee n switched off at a defined voltage to avoid a parasitic switch-on of the igbt.during turn-off, the gate voltage is monitored and the clamp output is activated when the gate voltage goes below 2 v above vee2.
eicedriver? 1ED020I12-BT pin configuration and func tionalitypin functionality final data sheet 13 rev 2.0, 2012-07-31 gnd2 reference ground reference ground of the output chip. out driver output output pin to drive an igbt. the voltage is switched between vee2 and vcc2. in normal operating mode vout is controlled by in+, in- and /rst. during error mode (uvlo, internal error or desat) vout is set to vee2 independent of the input control signals. vcc2 positive power supply pin of the output side. tlset two level turn off adjust circuitry at tlset adjust th e two level turn off time with an external capacitor to gnd2 and the two level voltage with an external zener diode to gnd2, for wave forms please see figure 9 .
eicedriver? 1ED020I12-BT functional descriptionintroduction final data sheet 14 rev 2.0, 2012-07-31 4 functional description 4.1 introduction the 1ED020I12-BT is an advanced igbt gate driver for motor drives typical greater 10 kw. control and protection functions are included to make possible the design of high reliability systems. the device consists of two galvanic se parated parts. the input chip can be directly connected to a standard 5 v dsp or microcontroller with cmos in/output and the output chip is connected to the high voltage side. an effective active miller cl amp function avoids the need of negative gate driving in some applications and allows the use of a simple bootstrap supply for the high side driver. a rail-to-rail driver output enables the user to provide ea sy clamping of the igbts gate voltage during short circuit of the igbt. so an increase of short circuit current due to the feedback vi a the miller capacitan ce can be avoided. further, a rail-to-rail output reduces power dissipation. the device also includes an igbt desatura tion protection with a /flt status output. a two-level turn-off feature with adjustab le delay protects against excessive overvoltage at turn-off in case of overcurrent or short circuit condition. the same delay is applied at turn-on to prevent pulse width distortion. a ready status output reports if the de vice is supplied and operates correctly. figure 4 application ex ample bipolar supply 4.2 supply the driver 1ED020I12-BT is designed to support two diffe rent supply configurations, bipolar supply and unipolar supply. in bipolar supply the driver is typi cally supplied with a positive voltage of 15v at vcc2 and a negative voltage of -8v at vee2, refer to figure 4 . negative supply prevents a dynamic turn on due to the additional charge which is generated from igbt input capacitance times negative su pply voltage. if an appropriate negative supply voltage is used, connecting clamp to igbt gate is r edundant and therefore typically not necessary. for unipolar supply configuration the driver is typically supplied with a positive voltage of 15v at vcc2. erratically dynamic turn on of the igbt could be prevented with active miller clamp function, so clamp output is directly connected to igbt gate, refer to figure 5 . gnd1 in+ in- rdy /flt /rst vcc1 out vcc2 gnd2 clamp desat +5v vee 2 sgnd in+ rdy flt rst +15v -8v tlset 1k 10k 10k 10r 220p 47p 10v 1 1 100n
eicedriver? 1ED020I12-BT functional descriptioninternal protection features final data sheet 15 rev 2.0, 2012-07-31 figure 5 application exam ple unipolar supply 4.3 internal protection features 4.3.1 undervoltage lockout (uvlo) to ensure correct switching of igbts the device is equi pped with an undervoltage lockout for both chips, refer to figure 13 and figure 14 . if the power supply voltage v vcc1 of the input chip drops below v uvlol1 a turn-off signal is sent to the output chip before power-down. the igbt is switched off and th e signals at in+ and in- are ignored as long as v vcc1 reaches the power-up voltage v uvloh1 . if the power supply voltage v vcc2 of the output chip goes down below v uvlol2 the igbt is switched off and signals from the input chip are ignored as long as v vcc2 reaches the power-up voltage v uvloh2 . vee2 is not monitored, otherwise negative supply voltage range fr om 0 v to -12 v would not be possible. 4.3.2 ready status output the ready output at pin /rdy shows the stat us of three internal protection features. ? uvlo of the input chip ? uvlo of the output chip after a short delay ? internal signal transmission after a short delay it is not necessary to reset the read y signal since its state only depends on the status of the former mentioned protection signals. 4.3.3 watchdog timer during normal operation the internal signal transmission is monitored by a watchdog time r. if the transmission fails for a given time, the igbt is switched off an d the ready output reports an internal error. 4.3.4 active shut-down the active shut-down feature ensures a safe igbt off-state if the outp ut chip is not connected to the power supply, igbt gate is cl amped at out to vee2. gnd1 in+ in- rdy /flt /rst vcc1 out vcc2 gnd2 clamp desat +5v vee 2 sgnd in+ rdy flt rst +15v tlset 1k 10k 10k 10r 220p 47p 10v 1 100n
eicedriver? 1ED020I12-BT functional descriptionnon-inverting and inverting inputs final data sheet 16 rev 2.0, 2012-07-31 4.4 non-inverting and inverting inputs there are two possible input modes to control the igbt. at non-inverting mode in+ contro ls the driver output while in- is set to low. at inverting mo de in- controls the driver output while in+ is set to high, refer to figure 7 . a minimum input pulse width is defined to filter occasional glitches. 4.5 driver output the output driver section uses only mosfets to provide a rail-to-rail output. this feature permits that tight control of gate voltage during on-state and sh ort circuit can be maintained as long as the drivers supply is stable. due to the low internal voltage drop , switching behaviour of the igbt is pre dominantly governed by the gate resistor. furthermore, it reduces the power to be dissipated by the driver. 4.6 two-level turn-off the two-level turn-off introduces a second turn off volt age level at the driver output in between on- and off- level, refer to figure 8 . this additional le vel ensures lower v ce overshoots at turn off by reducing gate emitter voltage of the igbt at short circuits or over current events. the v ge level is adjusting the current of the igbt at the end two level turn off interval, the required timing is depending on stray inductance and over current at beginning of two level turn off interval. reference voltage level and hold up time could be adjus ted at tlset pin. the reference voltage is set by the required zener diode connected between pin tlset and gnd2. the holdup time is set by the capacitor connected to the same pin tlset and gnd2. the hold time can be adjusted during switch on using the whole capacitance connected at pin tlset including capacitor, parasitic wiring capacitance and junction capacitance of zener dio de. when a switch on signal is given the ic starts to discharge c tlset . discharging c tlset is stopped after 500 ns. then ctlset is charged with an internal charge current i tlset . when the voltage of the capacitor c tlset exceeds 7 v a second current source starts charging c tlset up to v zdiode . at the end of this discharge-charge cyc le the gate driver is switched on. the time between in initiated switch- on signal (minus an internal propagati on delay of approximately 200 ns) and switch-on of the gate drive is sampled and stored digitally. it represents the two level turn off set time t tlset during switch-off. due to digitalization the tpdon time can vary in time steps of 50 ns. if switch off is initiated from in+, in- or /rst signal , the gate driver is switched off immediately after internal propagation delay of approximately 200 ns and v out begins to decrease to the second gate voltage level. for switch off initiate d by desat, the gate driver switch off is delayed by des aturation sense to out delay, afterwards v out begins to decrease to the second gate voltage level. for reaching second gate voltage level the output voltage v out is sensed and compared with the zener voltage v zdiode . when v out falls below the reference voltage v zdiode of the zener diode the switch off process is interrupted and v out is adjusted to v zdiode . out is switched to vee2 after the holdup time has passed. the two-level turn-off function cannot be disabled.
eicedriver? 1ED020I12-BT functional descriptionminimal on time / off time final data sheet 17 rev 2.0, 2012-07-31 4.7 minimal on time / off time the 1ED020I12-BT driver requires minimal on and off time for proper operation in the application. minimal on time must be greater than the adjustable two level plateau time t tlset , shorter on times will be suppressed by generating of the plateau time refer to figure 10 . due to the short on time, the voltage at tlset pin does not reach the comparator threshold; therefore the driver does not turn on. a similar principle takes place for off time. minimal off time must be greater than t tlset ; shorter off times will be suppre ssed, which means out stays on refer to figure 11 . a two level turn off plateau cannot be shortened by the driver. if the driver has entered the turn off sequence it cannot switch off due to the fact, that th e driver has already entered the shut off mode. but if the driver input signal is tu rned on agai n, it will leave the lower level after t tlset time by switching out to high, refer to figure 12 . 4.8 external protection features 4.8.1 desaturation protection a desaturation protection ensures the protection of the igbt at short circuit. when the desat voltage goes up and reaches 9 v, the output is driven low, refer to figure 9 . further, the /flt output is activated. a programmable blanking time is used to allow enough time for igbt satu ration. blanking time is provided by a highly precise internal current source and an external capacitor. 4.8.2 active miller clamp in a half bridge configuration the switched off igbt tends to dynamically turn on during turn on phase of the opposite igbt. a miller clamp allows sinking the miller current across a low impedance path in this high dv/dt situation. therefore in many applications, the us e of a negative supply vo ltage can be avoided. during turn-off, the gate voltage is monitored and the clam p output is activated when the gate voltage goes below typical 2 v (related to vee2). the clamp is designed for a miller current up to 2 a. 4.8.3 short circuit clamping during short circuit the igbts gate vo ltage tends to rise because of the feedback via the miller capacitance. an additional protection circuit connected to out and clamp lim its this voltage to a value slightly higher than the supply voltage. a current of maximum 500 ma for 10 s may be fed back to the supply through one of this paths. if higher currents are expected or a tighter clampi ng is desired external schottky diodes may be added. 4.9 reset the reset input has two functions. firstly, /rst is in charge of setti ng back the /flt output. if /rst is lo w longer than a given time, /flt will be cleared at the rising edge of /rst, refer to figure 9 ; otherwise, it will remain un changed. moreov er, it works as enable/shutdown of the input logic, refer to figure 7 .
eicedriver? 1ED020I12-BT electrical parametersab solute maximum ratings final data sheet 18 rev 2.0, 2012-07-31 5 electrical parameters 5.1 absolute maximum ratings note: absolute maximum ratings are defi ned as ratings, which when being exceeded may lead to destruction of the integrated circuit. unless otherwise noted all parameters refer to gnd1. table 2 absolute maximum ratings parameter symbol values unit note / test condition min. max. positive power supply output side v vcc2 -0.3 20 v 1) 1) with respect to gnd2. negative power supply output side v vee2 -12 0.3 v 1) maximum power supply voltage output side (v vcc2 - v vee2 ) v max2 ?28v? gate driver output v out v vee2 -0.3 v max2 +0.3 v ? gate driver high output maximum current i out ? 2.4 a t = 2 s gate & clamp driver low output maximum current i out ? 2.4 a t = 2 s maximum short circuit clamping time t clp ?10 s i clamp/out = 500 ma positive power supply input side v vcc1 -0.3 6.5 v ? logic input voltages (in+,in-,rst ) v logicin -0.3 6.5 v ? opendrain logic output voltage (flt ) v flt# -0.3 6.5 v ? opendrain logic output voltage (rdy) v rdy -0.3 6.5 v ? opendrain logic output current (flt ) i flt# ?10ma? opendrain logic output current (rdy) i rdy ?10ma? pin desat voltage v desat -0.3 v vcc2 +0.3 v 1) pin clamp voltage v clamp -0.3 v vcc2 +0.3 2) 2) may be exceeded during short circuit clamping. v 3) 3) with respect to vee2. junction temperature t j -40 150 c ? storage temperature t s -55 150 c ? power dissipation, per input part p d, in ? 100 mw 4) @ t a = 25c power dissipation, per output part p d, out ? 700 mw 4) @ t a = 25c thermal resistance (input part) r thja,in ? 160 k/w 4) @ t a = 25c thermal resistance (output chip active) r thja,out ? 125 k/w 4) @ t a = 25c esd capability v esd ? 1.5 kv human body model 5)
eicedriver? 1ED020I12-BT electrical parameters operating parameters final data sheet 19 rev 2.0, 2012-07-31 5.2 operating parameters note: within the operating range the ic operates as de scribed in the functional description. unless otherwise noted all parameters refer to gnd1. 5.3 recommended operating parameters note: unless otherwise noted all parameters refer to gnd1. 4)output ic power dissipation is der ated linearly at 10 mw/c above 62c . input ic power dissipation does not require derating. see figure 17 for reference layouts for these thermal data. thermal performance may change significantly with layout and heat dissi pation of components in close proximity. 5) according to eia/jesd22-a114-b (discharging a 100 pf capacitor through a 1.5 k ? series resistor). table 3 operating parameters parameter symbol values unit note / test condition min. max. positive power supply output side v vcc2 13 20 v 1) 1) with respect to gnd2. negative power supply output side v vee2 -12 0 v 1) maximum power supply voltage output side ( v vcc2 - v vee2 ) v max2 ?28v? positive power supply input side v vcc1 4.5 5.5 v ? logic input voltages (in+,in-,rst) v logicin -0.3 5.5 v ? pin clamp voltage v clamp v vee2 -0.3 v vcc2 2) 2) may be exceeded during short circuit clamping. v? pin desat voltage v desat -0.3 v vcc2 v 1) pin tlset voltage v tlset -0.3 v vcc2 v 1) ambient temperature t a -40 105 c ? common mode transient immunity 3) 3) the parameter is not subject to production test - verified by design/characterization |d v iso /dt| ? 50 kv/ s@ 500v table 4 recommended operating parameters parameter symbol value unit note / test condition positive power supply output side v vcc2 15 v 1) 1) with respect to gnd2. negative power supply output side v vee2 -8 v 1) positive power supply input side v vcc1 5v?
eicedriver? 1ED020I12-BT electrical parameterselectrical characteristics final data sheet 20 rev 2.0, 2012-07-31 5.4 electrical characteristics note: the electrical characteri stics include the spread of values in supply voltages, load and junction temperatures given below. typical values represent the median values at t a = 25c. unless otherwise noted all voltages are given with respect to their re spective gnd (gnd1 for pins 9 to 16, gnd2 for pins 1 to 8). 5.4.1 voltage supply table 5 voltage supply parameter symbol values unit note / test condition min. typ. max. uvlo threshold input chip v uvloh1 ?4.14.3v? v uvlol1 3.5 3.8 ? v ? uvlo hysteresis input chip ( v uvloh1 - v uvlol1 ) v hys1 0.15 ? ? v ? uvlo threshold output chip v uvloh2 ? 12.0 12.6 v ? v uvlol2 10.4 11.0 ? v ? uvlo hysteresis output chip ( v uvloh1 - v uvlol1 ) v hys2 0.7 0.9 ? v ? quiescent current input chip i q1 ?79ma v vcc1 =5 v in+ = high, in- = low =>out = high, rdy = high, /flt = high quiescent current output chip i q2 ?4.56ma v vcc2 =15 v v vee2 =-8 v in+ = high, in- = low =>out = high, rdy = high, /flt = high
eicedriver? 1ED020I12-BT electrical parameterselectrical characteristics final data sheet 21 rev 2.0, 2012-07-31 5.4.2 logic input and output table 6 logic input and output parameter symbol values unit note / test condition min. typ. max. in+,in-, rst low input voltage v in+l , v in-l , v rstl# ??1.5v? in+,in-, rst high input voltage v in+h , v in-h , v rsth# 3.5??v? in-, rst input current i in- , i rst# -400 -100 ? a v in- = gnd1 v rst# = gnd1 in+ input current i in+ , ? 100 400 a v in+ = vcc1 rdy,flt pull up current i prdy , i pflt# -400 -100 ? a v rdy = gnd1 v flt# = gnd1 input pulse suppression in+, in- t minin+ , t minin- 30 40 ? ns ? input pulse suppression rst for enable/shutdown t minrst 30 40 ? ns ? pulse width rst for reseting flt t rst 800??ns? flt low voltage v fltl ??300mv i sink(flt#) = 5 ma rdy low voltage v rdyl ??300mv i sink(rdy) = 5 ma
eicedriver? 1ED020I12-BT electrical parameterselectrical characteristics final data sheet 22 rev 2.0, 2012-07-31 5.4.3 gate driver 5.4.4 active miller clamp table 7 gate driver parameter symbol values unit note / test condition min. typ. max. high level output voltage v outh1 v vcc2 -1.2 v vcc2 -0.8 ? v i outh = -20 ma v outh2 v vcc2 -2.5 v vcc2 -2.0 ? v i outh = -200 ma v outh3 v vcc2 -9 v vcc2 -5 ? v i outh = -1 a v outh4 ? v vcc2 -10 ? v i outh = -2 a high level output peak current i outh -1.5 -2.0 ? a in+ = high, in- = low; out = high low level output voltage v outl1 ? v vee2 +0.04 v vee2 +0.09 v i outl = 20 ma v outl2 ? v vee2 +0.3 v vee2 +0.85 v i outl = 200 ma v outl3 ? v vee2 +2.1 v vee2 +5.0 v i outl = 1 a v outl4 ? v vee2 +7 ? v i outl = 2 a low level output peak current i outl 1.5 2.0 ? a in+ = low, in- = low; out = low, v vcc2 =15 v, v vee2 =-8 v table 8 active miller clamp parameter symbol values unit note / test condition min. typ. max. low level clamp voltage v clampl1 ? v vee2 +0.03 v vee2 +0.08 v i outl = 20 ma v clampl2 ? v vee2 +0.3 v vee2 +0.8 v i outl = 200 ma v clampl3 ? v vee2 +1.9 v vee2 +4.8 v i outl = 1 a low level clamp current i clampl 2??a 1) 1) the parameter is not subject to production test - verified by design/characterization clamp threshold voltage v clamp 1.6 2.1 2.4 v related to vee2
eicedriver? 1ED020I12-BT electrical parameterselectrical characteristics final data sheet 23 rev 2.0, 2012-07-31 5.4.5 short circuit clamping 5.4.6 dynamic characteristics dynamic characteristics are measured with v vcc1 = 5 v, v vcc2 = 15 v and v vee2 = -8 v. table 9 short circuit clamping parameter symbol values unit note / test condition min. typ. max. clamping voltage (out) ( v out - v vcc2 ) v clpout ? 0.8 1.3 v in+=high, in- = low, out = high i out = 500 ma (pulse test, t clpmax = 10 s) clamping voltage (clamp) ( v vclamp - v vcc2 ) v clpclamp ? 1.3 ? v in+ = high, in- = low, out = high i clamp = 500 ma (pulse test, t clpmax = 10 s) clamping voltage (clamp) v clpclamp ? 0.7 1.1 v in+ = high, in- = low, out = high i clamp = 20 ma table 10 dynamic characteristics parameter symbol values unit note / test condition min. typ. max. in+, in- input to output propagation delay on and off t pdon 1.5 1.75 2.0 s c tlset = 0, t a = 25c in+, in- input to output propagation delay distortion ( t pdoff - t pdon ) t pdisto -40 -10 20 ns c tlset = 0, t a = 25c in+, in- input to output propagation delay on variation due to temp t pdont ??200ns 1) c tlset = 0 in+, in- input to output propagation delay off variation due to temp t pdofft ??230ns 1) c tlset = 0 in+, in- input to output propagation delay distortion variation due to temp ( t pdoff - t pdon ) t pdistot ??25ns 1) c tlset = 0 rise time t rise 10 30 60 ns c load = 1 nf, v l 10%, v h 90% 150 400 800 ns c load = 34 nf v l 10%, v h 90%
eicedriver? 1ED020I12-BT electrical parameterselectrical characteristics final data sheet 24 rev 2.0, 2012-07-31 5.4.7 desaturation protection fall time t fall 10 20 40 ns c load = 1 nf v l 10%, v h 90% 100 250 500 ns c load = 34 nf v l 10%, v h 90% 1) the parameter is not subject to production test - verified by design/characterization table 11 desaturation protection parameter symbol values unit note / test condition min. typ. max. blanking capacitor charge current i desatc 450 500 550 a v vcc2 =15 v, v vee2 =-8 v v desat = 2 v blanking capacitor discharge current i desatd 11 15 ? ma v vcc2 =15 v, v vee2 =-8 v v desat =6 v desaturation reference level v desat 8.5 9 9.5 v v vcc2 =15 v desaturation sense to out tlto t desatout ?250320ns v out =90% c load = 1 nf desaturation sense to flt low delay t desatflt ??2.25 s v flt # =10%; i flt # =5 ma desaturation low voltage v desatl 40 70 110 mv in+=low, in-=low, out=low table 10 dynamic characteristics (cont?d) parameter symbol values unit note / test condition min. typ. max.
eicedriver? 1ED020I12-BT electrical parameterselectrical characteristics final data sheet 25 rev 2.0, 2012-07-31 5.4.8 active shut down 5.4.9 two-level turn-off table 12 active shut down parameter symbol values unit note / test condition min. typ. max. active shut down voltage v actsd 1) 1) with refe rence to vee2 ??2.0v i out = -200 ma, v cc2 open table 13 two-level turn-off parameter symbol values unit note / test condition min. typ. max. external reference voltage range (zener-diode) v zdiode 7.5 ? v cc2 -0.5 v ? reference voltage for setting two-level delay time v tlset 6.6 7 7.3 v ? current for setting two-level delay time and external reference voltage (zener-diode) i tlset 420 500 550 a v tlset = 10 v external capacitance range c tlset 0?220pf?
eicedriver? 1ED020I12-BT insulation characteristicscertified according to din en 60747-5-2 (vde 0884 final data sheet 26 rev 2.0, 2012-07-31 6 insulation characteristics insulation characteristics are guaranteed only withi n the safety maximum ratings which must be ensured by protective circuits in application. surface mount cl assification is class a in accordance with ceccoo802. this coupler is suitable for ?b asic insulation? only within the safety rati ngs. compliance with the safety ratings shall be ensured by means of suitable protective circuits. 6.1 certified according to din en 60747- 5-2 (vde 0884 teil 2): 2003-01. basic insulation 6.2 recognized under ul 1577 6.3 reliability for qualification report please contact your local infineon technologies office. table 14 according to din en 60747-5-2 description symbol characteristic unit installation classification per en 60664-1, table 1 for rated mains voltage 150 v rms for rated mains voltage 300 v rms for rated mains voltage 600 v rms i-iv i-iii i-ii ? climatic classification 40/105/21 ? pollution degree (en 60664-1) 2 ? minimum external clearance clr 8.12 mm minimum external creepage cpg 8.24 mm minimum comparative tracking index cti 175 ? maximum repetitive insulation voltage v iorm 1420 v peak input to output test voltage, method b 1) v iorm *1.875= v pr , 100% production test with t m = 1 sec, partial discharge < 5 pc 1) refer to vde 0884 for a detailed de scription of method a and method b partial discharge test profiles. v pr 2663 v peak input to output test voltage, method a 1) v iorm *1.6= v pr , 100% production test with t m =60sec, partial discharge < 5 pc v pr 2272 v peak highest allowable overvoltage v iotm 6000 v peak maximum surge insulation voltage v iosm 6000 v insulation resistance at t s, v io = 500 v r io > 10 9 ? table 15 recognized under ul 1577 description symbol characteristic unit insulation withstand voltage / 1 min v iso 3750 v rms insulation test voltage / 1 s v iso 4500 v rms
eicedriver? 1ED020I12-BT timing diagramsreliability final data sheet 27 rev 2.0, 2012-07-31 7timing diagrams all diagrams related to the two-level switch-off feature figure 6 propagation delay, rise and fall time figure 7 principle switching behavior figure 8 typical switching behavior in+ out t pd on 50 % 50 % t pd off 10 % 90 % t rise t fall out /rst in+ in- out tlset in+ t pd on ad j t ad j 1 v zdiode v zdiode t tlset t pd t tlfall t pd t tlset v tlset , typ. 7v
eicedriver? 1ED020I12-BT timing diagramsreliability final data sheet 28 rev 2.0, 2012-07-31 figure 9 desat switch-off behavior figure 10 short switch on pulses v d esat typ. 9v >t rstmin out desat in+ /flt /rst t pd on t desatflt t desatflt t d esatou t t tlset t desatout t tlset out tlset in+ t pd on t pd o ff t pd on t pd t tlset t tlset t tlset t pd
eicedriver? 1ED020I12-BT timing diagramsreliability final data sheet 29 rev 2.0, 2012-07-31 figure 11 short switch off pulses figure 12 short switch off pulses, ringing surpression out tlset in+ t pd off t pd off t pd o n t pd t pd t pd on t pd off t tlset t tlset t tl set out tlset in+ t pd on t pd off t pd t pd off t pd off t pd on t pd forced turn off after three consecutive on - cycles t tlset t tlset t tlset t tlset
eicedriver? 1ED020I12-BT timing diagramsreliability final data sheet 30 rev 2.0, 2012-07-31 figure 13 vcc2 ramp up figure 14 vcc2 ramp down and vcc2 drop out in+ vcc2 v uvloh2 i desat t pd on t pd off rdy vz out tlset in+ vcc2 v uvloh2 rdy /flt v uvlol2 t tlset t pd on t pd d t pd d t pd d
eicedriver? 1ED020I12-BT timing diagramsreliability final data sheet 31 rev 2.0, 2012-07-31 figure 15 typical t tlset time over c tlset capacitance 5 4 3 2 1 t tl set [usec] 50 100 150 200 c tlset [pf] 0 0
eicedriver? 1ED020I12-BT package outlinesreliability final data sheet 32 rev 2.0, 2012-07-31 8 package outlines figure 16 pg-dso-16-15 (plastic (green) dual small outline package) 0.412 0.104 0.019 0.013 0.410 0.299 0.040 millimeters l h d dim a1 a b c e e1 n e - min 16 0.024 0 8 0.29 max inches 16 0.050 bsc 0.402 min - 0.005 0.014 0.009 0.400 0.292 max 0.011 scale 1.0 0 2mm 0 1.0 0.12 2.64 0.48 0.32 10.47 10.41 7.59 7.42 10.16 10.21 0.23 0.35 1.02 0.61 8 0 1.27 bsc 02 issue date 31.07.2012 document no. z8b00166131 european projection revision 0.016 0.010 0.41 0.25
eicedriver? 1ED020I12-BT application notesreference layout for thermal data final data sheet 33 rev 2.0, 2012-07-31 9 application notes 9.1 reference layout for thermal data the pcb layout shown in figure 17 represents the reference layout used for the thermal characterisation. pins 9 and 16 (gnd1) and pins 1 and 8 ( vee2) require ground pla ne connections for achiving maximum power dissipation. the 1ED020I12-BT is conceived to dissipat e most of the heat generated through this pins. figure 17 reference layout for thermal data (copper thickness 102 m) 9.2 printed circuit board guidelines following factors should be taken into account for an optimum pcb layout. ? sufficient spacing should be kept between high vo ltage isolated side and low voltage side circuits. ? the same minimum distance between two adjacent high-side isolated parts of the pcb should be maintained to increase the effective isolat ion and reduce parasitic coupling. ? in order to ensure low supply ripple and clean switching signals, bypass c apacitor trace lengths should be kept as short as possible. ? lowest trace length for vee2 to gnd2 decoupling coul d be achieved with capacitor closed to pins 1 and 3. bottom layer top layer
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